This invention relates to techniques used for testing integrated circuits and, more particularly, to a method for identifying a faulty cell in a chain of cells forming a shift register in a functional element, each cell being formed of a linked pair of latches.
As is well known, the principal obstacle to testing integrated circuits, particularly large-scale integrated (LSI) circuits, in a given functional element (chip, module, board or system) is the inaccessibility of internal signals, especially the nodes of the network. Prior test techniques involve complex sequential patterns intended to exercise all the internal circuits and transfer the results to the output pins of the functional element for observation.
With today's highly complex functional elements, however, these test techniques have become unsatisfactory because they take too much time, are too costly, and are generally inefficient.
One solution to this problem is embodied in a test technique based upon an approach called "Level-Sensitive Scan Design" (LSSD), as described in U.S. Pat. Nos. 3,783,254, 3,784,907 and 3,961,252, assigned to the assignee of the present invention. The LSSD technique enables testing problems to be solved at all levels of packaging. This technique permits every functional element to be completely tested and even allows a complex system to be diagnosed at the customer's site by a field-service engineer. As used herein, the term "functional element" essentially means a chip or a module, but could also apply to a board or a system.
The principles of the LSSD technique as used to test integrated circuits are described in an article by Neil C. Berglund entitled "Level-Sensitive Scan Design Tests Chips, Boards, Systems" published in Electronics, Mar. 15, 1979, pp. 108-110. This article is incorporated herein by reference.
The lowest level of packaging is the chip. As is well known, this is a silicon slice containing several thousands of elementary components, such as transistors, diodes and resistors, interconnected to form hundreds of circuits capable of performing desired logic functions. Several chips are assembled onto a ceramic substrate provided with input/output pins for establishing electrical connections with the outside world. The substrate is encapsulated into a module. Several modules are in turn mounted into a printed circuit board. Lastly, at the highest level of packaging, several boards may be interconnected to form a system.
With LSSD, a chip may comprise several combinatorial logic blocks each of which is associated with a storage cell consisting of a latch called a Shift Register Latch (SRL). A single long shift register termed an "LSSD chain" is formed by chaining a number of such cells or SRLs together. Each SRL, which is actually a pair of bistable latches designated L1, L2, forms a single stage of the shift register.
The L1 latch can be set from two sources by two different clock signals, A and C, applied to clock inputs A and C, with the latter input receiving system clock signals. Latch L1 also has a data input, Data In (DI), and a test input called Scan Data In (SDI). Test patterns consisting of binary words are applied to the SDI pin of the chip. Latch L2 has a data input connected to one of the outputs of the associated L1 latch, and an input that receives B clock signals causing the output data from L1 to be transferred into L2.
The long shift register referred to above is formed by connecting the output of the L2 latch in the first SRL (forming the first stage of the register) to the input of the L1 latch in the next SRL, and so on, down to the last SRL. The test input, SDI, of the L1 latch in the first SRL is connected to the SDI pin, or main input, of the chip, and the output of the L2 latch in the last SRL is connected to an output pin, designated Scan Data Out (SDO), or main output, of the chip. The A, B and C clock inputs of each SRL are connected to chip input pins so designated. Obviously, the "chain" concept is also applicable to functional elements of the same type or different types.
It should be noted that while the latches forming the LSSD chains may represent as much as 40% of the surface area of a logic chip, most of these are used to implement the normal system function.
Bits are transferred through the SRL in two steps. A bit applied to the test input, SDI, of latch L1 is loaded therein by the A clock pulse, and the same bit is obtained at the output of the L2 latch at the occurrence of the B clock pulse. A number of pairs of A and B clock pulses equivalent to the number of SRLs is required in order for a signal applied to the SDI input of a functional element to be transferred to the SDO output thereof. In this mode of operation, system clock C is not pulsed.
To test a functional element, a static test called a "flush" test is first performed. To this end, an active potential, for example a high logic level, is applied to the A and B clock inputs (A=B=1), while the C clock input receives a low logic level (C=0). A square pulse is applied to the SDI input of the chain to be tested and is retrieved at the SDO output after a predetermined time interval has elapsed. This is a combinatorial type of static test in which every latch in the LSSD chain acts as an inverter so that the chain operates as a series of inverters rather than as a shift register. As a result, the data pulse applied to input SDI is obtained at output SDO of the chain after a time interval equal to the accumulated response times of all the SRLs in the chain has elapsed. In addition to providing useful information on the propagation times, the flush test determines whether the LSSD chain is functioning properly.
A dynamic test called a "scan" test is next performed, in which the C clock input is maintained at a low logic level while pulsing the A and B clocks (which are not simultaneously activated). The LSSD chain then acts as a shift register. This test serves to establish that the chain is not operating properly if the data pulse applied to the SDI input fails to be transferred to the SDO output when clock pulses are applied to the A and B clock inputs
Lastly, a functional test is performed in the scan mode. Briefly, a test pattern (a series of binary data) is applied to the SDI input and the A and B clocks are pulsed to transfer the test pattern into the SRLs. All the latches in the functional element having thus been initialized, logic data are present on the parallel output pins of the element. By applying stimuli to the parallel input pins of the element and by pulsing the C clock, a binary word reflecting some particular state of the combinatorial logic is loaded in the LSSD chain. The output pins can then be observed to determine if the combinatorial logic is functioning properly and the results are compared with the expected state of the SRLs, as determined by a computer simulation model (see FIG. 2 of the article referred to earlier). In this manner, the logic on the functional element is tested for typically 98% to 100% of all DC faults with program-generated test data.
In actual practice, the flush test is preceded by a parametric test that consists of determining such analog values as current consumption, leakage currents, and the like.
The object of the flush and scan tests is to determine if the LSSD chains are functioning properly. If such is the case, and if no short circuits or open circuits exist in the connections between the latches or in the clock pulse distribution circuits, then a functional test of the combinatorial logic itself is performed.
Since the LSSD chains, as described above, may represent up to 40% of the chip's surface area, and since a typical chain may comprise anywhere from 20 to 250 cells or SRLs, the probability of at least one failure occurring in a chain is far from negligible. Further, because the SRLs usually are scattered on the chip's surface, it is extremely difficult to quickly identify a faulty SRL, either during manufacturing or in field service, and to take remedial action. Thus, known tests of the flush or scan type can only provide information of a general nature, such as whether the LSSD chain is functioning properly or improperly. In the latter case, there was heretofore no way of identifying the faulty cell(s) in the chain, thus, the entire functional element had to be discarded.
Accordingly, there is a need for a test technique more refined than either the flush test or the scan test to permit faulty cells to be precisely identified so that remedial action can be taken during circuit fabrication. For example, if chips from different wafers should all be found to have the same faulty cell, this could probably be ascribed to some defect in the lithographic mask used to fabricate these wafers. In addition, the desired test technique should allow faulty cells to be identified regardless of the type of functional element (chip, module, etc.) involved. Lastly, the test technique should be simple, accurate and relatively inexpensive.